1. Technical Field
The present invention relates to semiconductor memories, and more particularly, to layouts of a decoder in a volatile semiconductor memory device.
2. Discussion of Related Art
Performance trends of electronic systems, such as personal computers or communication devices, have led to high speed and high integration volatile semiconductor memories such as static random access memories (RAMs). More particularly, memory chip manufacturers have developed layout and fabrication techniques for memory cells as critical dimensions have decreased and as functional circuits have been implemented. As process techniques have been developed for reduced critical dimensions, techniques of laying out circuit wirings for peripheral circuits adjacent to a cell area, e.g., circuits in a functional circuit area called a cell core area, have become important in achieving higher integration circuits. A core logic, e.g., a section row decoder, functioning as an interface circuit needed to operate a unit memory cell is an example of a circuit laid out in the functional circuit area.
Within such devices (e.g., a section row decoder), to achieve high speed, read/write operations are performed in parallel with each other in one clock period or cycle. In the case of such semiconductor memory devices, circuits laid out in the functional circuit area become more complex, increasing a layout area. In addition, crosstalk caused by power and signal lines increases.
FIG. 1 is a timing diagram illustrating a data access operation in a typical high speed semiconductor memory device, and more particularly, a timing of a read pulse RD_WL and a write pulse WR_WL simultaneously applied to a word line in one clock period (Tc). A period T1 indicates a time period in which the read pulse is applied to the word line, and a period T2 indicates a read recovery time. Further, a period T3 indicates a time period in which the write pulse is applied to the word line and a period T4 indicates a write recovery time.
FIG. 2 is a diagram illustrating a configuration of a memory mat of a device to which the timing of FIG. 1 is applicable. Referring to FIG. 2, the memory mat, constituting a memory cell array, includes a plurality of blocks. Each block is divided into two memory blocks 100 and 110 by a section row decoder 200. Two main read and write word lines MWL_READ and MWL_WRITE of a main row decoder are connected to the section row decoder 200 in each block. The section row decoder 200 is connected to memory cells via four section word lines at a left side and four section word lines at a right side. Two pair of section word lines SWL_W and two pair of section word lines SWL_X are in the same logic state within one block. The memory mat further includes a main word line decoder (MWL DEC).
When a design rule of 80 or less nanometers is applied, and the cell pitch of the SRAM cell is reduced, it can become difficult to lay out a circuit of a section row decoder to match the reduced cell pitch.
Therefore, a need exists for a decoder having a reduced layout area.